Advances in semiconductor design and fabrication methods enable increasing miniaturization of electronic circuits. Complete systems comprising microprocessors, communication logic and, in particular, memories can be found on a single semiconductor chip in this case. Such systems-on-a-chip (SOC) have a multiplicity of technologies that previously had a high space requirement as separate components on a circuit board.
Whereas in the past semiconductor chips were dominated by logic functions and separate memories were provided externally, modern integrated circuits increasingly require embedded memories on the semiconductor chip itself. Embedded memories may be present in semiconductor chips as different memory blocks in different sizes and forms. As a result of the integration of memories on a semiconductor chip, it is possible to save space and the speed of memory accesses can be increased as a result of obviating interfaces and speed-retarding factors such as circuit boards.
Embedded memories in a system-on-a-chip have to be very reliable and tested accordingly. Therefore, a memory self-test controller is usually provided in a system-on-a-chip having embedded memories, said controller being tailored to the embedded memories provided in the system. Such a memory self-test controller (BIST—built-in self-test) then carries out a memory self-test for example after the fabrication of the corresponding semiconductor chip or else each time the SOC is started up.
By way of example, the U.S. Pat. No. 6,681,354 B2 describes a semiconductor chip self-test apparatus that is controlled by means of an internal configurable bus. In this case, an FPGA (field-programmable gate array) carries out a memory test program in externally triggered fashion. After the end of the test, the corresponding FPGA is used to carry out further functions.
FIG. 1 schematically shows a semiconductor chip SOC having embedded memories M1, M2, M3 and a memory self-test controller BIST according to the prior art.
The semiconductor chip SOC or the system on a semiconductor chip has embedded memories M1, M2, M3 coupled to a bus system L, S, A. The embedded memories M1, M2, M3 each have addressable memory cells which are addressed via an address line A, and are written to or read from via a write/read bus or line L, S. The respective access direction of addressing A, reading L and writing S of the memories M1, M2, M3 is illustrated only by way of example in the figure.
Furthermore, a central chip controller device CPU is provided, which is likewise coupled to the bus system L, S, A for the purpose of addressing, writing and reading of the memories.
A memory self-test controller BIST is additionally provided, which is coupled to the memories M1, M2, M3 via the address bus and the write/read bus. The memory self-test controller BIST can be controlled by an external self-test control signal STS.
The external self-test control signal STS informs the memory self-test controller BIST that a memory self-test is to be carried out. This is generally done after production, but may also be done when the system on the semiconductor chip SOC is started up. After the memory self-test has been carried out by the memory self-test controller BIST, the latter returns a result FS for evaluation to an external test apparatus. The initiation of the memory self-test and the evaluation of the test results FS may also be effected by the chip controller device CPU, as indicated by the dashed lines.
Each of the embedded memories M1, M2, M3 is assigned a memory address range in the address space. This is illustrated schematically in FIG. 2.
The memory address range of a respective memory is defined by a beginning address and an end address. By way of example, the memory cells provided in the embedded memory M1, M2, M3 can be addressed by memory addresses lying between a beginning memory address AM1, AM2, AM3 and an end memory address EM1, EM2, EM3. Furthermore, addresses for registers BIST1, BIST2, BIST3 of the memory self-test controller BIST are kept available in the address space. By way of example, instructions or program codes for the memory test to be carried out are written to the registers BIST1, BIST2, BIST3 of the self-test controller BIST. The registers BIST1, BIST2, BIST3 also include the respective status of the tested memory M1, M2, M3 or the respective test result. Depending on how many embedded memories M1, M2, M3 are provided on a semiconductor chip, it is necessary in each case to provide and define address ranges for the memory self-test controller registers BIST, BIST2, BIST3. The data width and the storage capacity of the respective registers also depend on the embedded memories M1, M2, M3.
A corresponding method for the memory self-test and a semiconductor chip having embedded memories and a memory self-test controller according to the prior art are complex because parts of the address space are occupied by the registers of the self-test controller. Furthermore, a corresponding self-test controller according to the prior art can only be used for one type of semiconductor chips having embedded memories. The self-test controller thus has to be adapted if the memory configuration changes for example through the number or size of the memories.